### Busy Beaver nonregular machines for class TM(5)

This page explains nonregular Turing machines with 5 states, related to Busy Beaver problem.

Good definition and current state of the problem you may find on Heiner Marxen Busy Beaver page.

I will use NR abbreviation (NonRegular) for machines that can't be proved by my program.

I will use NR1 abbreviation (NonRegular1) for machines from NR, writing 1 to tape at first step.

I will use HNR abbreviation (HardlyNonRegular) for machines from NR1 that can't be proved in any way by me or my program.

Computer scanning with current version of my program for TM(5) gives 164 NR machines.

The machines writing 0 at first few steps must be ignored - they have some meaning only if we evaluate S(n), but if we evaluate Sigma(n) or try to prove infinitnes, these few steps do nothing and machine is isomorphic to some machine writing 1 at first step.

Computer scanning gives 110 NR1 machines.

These machines may be divided into groups with different behavior:

• SRec (shift recursive) machines form about 50% of NR.
It seems that all they may be proved by hand.
I have proofs for the following SRec machines:
• machine 5502432 from TM(5) subset dm_0.
• machine 764350 from subset dm_1.
• machine 1375027 from subset dm_2.
• machine 3470230 from subset dm_2.
• machine 3470440 from subset dm_2.
• N_2N and 3N machines are 3-linear sequences, but with little complex behavior than the machines, proved by methods TryL1Cnt and TryModFin.
They are easy provable by hand.
• BL_1 machines must be proved by my method TryBL_Proof.
But there is some hint in this method and i hope to improve it soon.
• BL_2 machines are more complex binary-linear sequences.
May be some bigger changes in TryBL method will solve these machines.
• proved - machines proved by the last version of the program and HuffStat database.
The changes are made after the scanning process was begin, so these machines will not occur in new full scanning list.

If we exclude from HNR machines, seeming to be easy provable (all upper subclasses, except BL_2),
in HNR remain only 43 machines !!!

#### Scanning results:

I separated scanning process for TM(5) into 3 parts to allow scanning on different computers.
The scanned sets are named dm_0, dm_1 and dm_2.

The lists of NR for these 3 subsets of TM(5) follows:

#### 1. Subset dm_0:

These machines reaches halt state from state B, tape value 0.

Nonregular machines:

```A0  A1   B0  B1   C0  C1   D0  D1   E0  E1   |    id    | type |SRcnt|          spectrum

C1L E1L  H1L D1L  D1R D0L  A1L E1R  B0L C0R  |   827123 | ---- |3000 |  0  2  6  5 10 13  2  6 23 20 33  8 19 27 48
C1L E0R  H1L C0R  D1R A0L  A1R D1R  A1L B0R  |  1668912 | ---- |3000 |  0  3  0 14  0  4  0 33  0 15  0 64  0 24  0
C1L A0R  H1L E1L  D1R B0L  A1R C1R  C0L D1L  |  2523420 | ---- |1946 |  0 40  0 44  6 50  6 54 10 51  7 67 11 53 16
C1L D0R  H1L E0L  D1R C1L  E1L A1R  B1L D0L  |  3911891 | ---- |1942 |  0  9  0  8  0 22  0 33  0 59  0 57  0 57  0
C1L B1L  H1L A0L  D1R C1L  A0L E0R  C1R E1R  |  5181384 | N_2N | 109 |  2  3  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L D1R  H1L D0R  D1R A1L  B0R E0R  A0L E1L  |  5502432 | SRec |   4 |  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A0R  H1L D0R  D1R E1L  B1R E0L  C0L A1R  |  5652268 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A1L  H1L E0R  D1R E1R  C0L D0R  A0L B0R  |  5940584 | SRec |   4 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A1L  H1L E0R  D1R B1R  A0L D0R  C0L B0R  |  5964302 | SRec |   4 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A1L  H1L D0L  D1R E0L  A1L C0R  C1R B0L  |  6311798 | ---- |3000 |  0  3  0 14  0  4  0 33  0 15  0 64  0 24  0
C1L B0R  H1L D0R  D1L A0R  E1R C0L  C1R E1R  |  7224038 | ---- |3000 |  0  3  0 13  0  4  0 34  0 13  0 57  0 18  0
C1L B0R  H1L A1R  D1L C1L  E1L D1R  B0R C0L  |  8903522 | N_2N |  95 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A0R  H1L E1R  D1L A1R  B1R C0L  B0R D0L  | 10009103 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A1R  H1L C1R  D1L E1L  B1R D1R  A0R C0L  | 10224040 |proved|  20 |  0  4  0  8  0  6  0  0  0  7  0 10  0  5  0
C1L A0R  H1L E0R  D1L A1R  B1R C0L  B0R A0L  | 10561107 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L E1R  H1L E0L  D1L C0L  A1R B1R  D1R A0R  | 10974233 |proved| 316 |  0  7  5 10  0 17  0  0  0  0  0 20  0  0  0
C1L E1R  H1L C1L  D1L C0L  A1R B0R  D1R A0R  | 10979960 |proved| 325 |  0  6  5  9  0 16  0  0  0  0  0 19  0  0  0
C1L E0R  H1L D0R  D1L A0L  A1R A1L  B1R D1R  | 11554135 |proved| 654 |  0  0  4  6  2  0  0  2  2  0  2  2  2  2  2
C1L B0R  H1L E1R  D1L A1L  A1R D0L  A0R C1R  | 11799516 | ---- |2046 |  0 36  0 40  6 46  6 50  9 47  9 64 16 50 14
C1L B0R  H1L C0R  D1L C0L  E0R C1L  A0R E1R  | 11997798 | ---- |3000 |  2  4  8  8 14 30 27 34 46 64 76 83 71 75 82
C1L A1L  H1L E0R  D1L C1R  E0R A0L  A1L B1R  | 12173159 | N_2N | 109 |  2  3  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A1R  H1L E1R  D1L E0R  A0R C0L  B0R D0L  | 13686778 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L D0R  H1L E1L  C1R A1R  E0L D1R  B1L C1L  | 14788712 | SRec |  10 |  0  3  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L D1R  H1L D0R  C1R A1L  B0R E0R  A0L E1L  | 14833341 | SRec |   4 |  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L D1R  H1L C0L  A1R C1L  E1R A0R  B1L E0L  | 18119527 | ---- |  39 |  0  6  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L C0L  H1L D1R  D0R C1L  B1R E1R  E1L A1L  | 21155496 | SRec |   3 |  0  3  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A0L  H1L C0L  D0R A1L  B1L E1R  D1R E0R  | 21181509 | ---- | 350 |  0  6  4  0  7  4  7  7 11  7 14 11 12 14 13
C1L E1R  H1L A1L  D0R D0L  B1L D1R  A1L A0R  | 21992948 |proved|1340 |  0  0  3 13  0  5  0 23  0  0  4 30  0  0  0
C1L E1R  H1L A1L  D0R D0L  B1L D1R  A0R A0R  | 21993025 |proved|1312 |  0  0  3 13  0  5  0 22  0  0  4 28  0  0  0
C1L E1R  H1L A1L  D0R D0L  B1L D1R  A0R A0L  | 21993204 |proved|1625 |  0  0  3 13  0  5  0 23  0  0  4 32  0  0  0
C1L B1L  H1L E0L  D0R C0L  A1R D1R  A0R B0L  | 22046343 | SRec |   4 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L E0R  H1L E1R  D0R A0L  A1L D1R  B0R C0L  | 22086142 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A0L  H1L A0R  D0R A1L  E0R D1R  A1L B0R  | 22109761 | ---- |3000 |  2  4  8  9 14 28 24 40 40 49 45 64 54 61 70
C1L E0L  H1L E1L  D0R A1L  A0L C1R  C1R B0L  | 22600133 | ---- |3000 |  0  7  4  6 10  0 16  0 21  4 27  6 33  6 35
C1L D1R  H1L E1L  D0R C0L  E1R A1R  A1L B1L  | 22976011 |proved|  32 |  0  5  4  0  4  9  2  7  5  8  4  0  2  8  8
C1L B0R  H1L A1R  D0L E1R  E0R C1L  C1R A0R  | 25621006 | ---- |3000 |  0  7  4  7 10  0 16  0 21  4 27  6 33  6 35
C1L A1R  H1L D1R  B0R E0L  A1R B0R  A1L E1L  | 26859019 | N_2N | 109 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A1R  H1L D1R  B0R E0L  A1L B0R  A1L E1L  | 26939795 | N_2N | 109 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A1R  H1L D1R  B0R E1L  C0L B1R  A0R E0L  | 27079513 | SRec |   4 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L D1L  H1L D0L  A0R C0L  E0R B0L  A1R E1R  | 28409414 | SRec |   4 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A1R  H1L E1R  A0R D1L  E0R D0L  C0L B1R  | 28501423 | SRec |   4 |  2  3  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A1R  H1L E0R  A0R D1L  C0L B0R  B1R D0L  | 28510651 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A1R  H1L E0R  A0R D1L  C0L B0R  B1R A0L  | 28510672 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0

Machines writing 0 at first step (eliminated):
C0L D1L  H1L A1L  D1R B0L  E1R C1R  C1L E0R  | 28827733 | ---- |2046 |  0 36  0 40  6 46  6 50  9 47  9 64 16 50 14
C0L D0R  H1L D1L  D1R C1L  E1R A1R  B1L E1L  | 28855197 | SRec |  20 |  0  4  0  8  0  6  0  0  0  7  0 10  0  5  0
C0L A1L  H1L D0L  D1R B0L  E1R D0R  A0L D1R  | 29230672 | ---- |3000 |  2  4  8  8 14 30 27 34 46 64 76 83 71 75 82
C0L D0R  H1L E1L  D1R C1L  A1R E0L  B0L A0R  | 30510645 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L B0R  H1L A0R  D1R B1R  E0L D0R  C1L E1L  | 31205809 | SRec |   4 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L C0R  H1L C1R  D1R A1L  E0L E0R  B1R E1L  | 31208319 | ---- |1625 |  0  0  3 13  0  5  0 23  0  0  4 32  0  0  0
C0L C0L  H1L C1R  D1R A1L  E0L E0R  B1R E1L  | 31208335 | ---- |1312 |  0  0  3 13  0  5  0 22  0  0  4 28  0  0  0
C0L A0R  H1L E1L  D1R C1L  B0L A1R  D0R B1L  | 31399596 | SRec |   4 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L B0R  H1L A0R  D1L C1L  E1R A1R  D0L E0R  | 31937656 | SRec |   4 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L A1L  H1L E0R  D1L E1R  E1R C1L  B0R A0R  | 32029629 | SRec |   4 |  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L A1L  H1L E0R  D1L E1R  D1R C1L  B0R A0R  | 32579735 | SRec |   4 |  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L E0R  H1L C0L  D1L B1L  A1R D1L  D1R E1R  | 33688612 | ---- | 109 |  2  3  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L A0R  H1L E0R  D1L C1L  A1R B1R  D0L B0R  | 33803876 | SRec |   4 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L D1R  H1L E1L  D1L E0L  A0R C1L  D1R B0L  | 34290421 | ---- |3000 |  0  7  4  6 10  0 16  0 21  4 27  6 33  6 35
C0L A0R  H1L D0R  A1R D1R  E0L B0R  C1L E1L  | 34509795 | SRec |   4 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L D1R  H1L E1L  A1R C1L  E0L D0R  A0R B1L  | 34918685 | SRec |   4 |  2  3  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L D1R  H1L E0L  A1R C1L  A0R B0L  B1L D0R  | 34932802 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L D1R  H1L E0L  A1R C1L  A0R B0L  B1L C0R  | 34932819 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L B1R  H1L A1R  D0R E1L  C1L D1R  A0R E0L  | 35487300 | SRec |   4 |  2  3  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L B0R  H1L E0R  D0R A1L  C1L D1R  B1R D0L  | 35493294 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L B0R  H1L E0R  D0R A1L  C1L D1R  B1R A0L  | 35493315 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L D1R  H1L E1R  D0R A1L  A1R E0R  A1L B0R  | 35609160 | ---- |3000 |  0  7  4  6 10  0 16  0 21  4 27  6 33  6 35
C0L A0R  H1L C1L  D0R B1L  E0L A1R  D1R E1L  | 35643503 | SRec |   4 |  2  3  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L E1R  H1L E0L  D0L C1L  E1R B0L  A1R E0R  | 35734559 | ---- |3000 |  2  4  8  8 14 30 27 34 46 64 76 83 71 75 82

```
NR_count =67
NR1_count=43
HNR_count=13

#### 1. Subset dm_1:

These machines reaches halt state from state A, tape value 1.

Nonregular machines:

```A0  A1   B0  B1   C0  C1   D0  D1   E0  E1   |    id    | type |SRcnt|          spectrum

B1L H1L  C1R A0L  E1L D1R  C0R B0L  D0R E0L  |   764350 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
B1L H1L  C1R A0L  C0L D0R  E0R C1L  A1L D1R  |  3788992 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
B1L H1L  C1R E0R  D1L B0R  D0L A1L  C0R A0L  |  5359517 | ---- |3000 |  0  6 10 14 17 21 22 23 30 24 35 48 42 31 28
B1L H1L  C1L B1R  D1R E1L  B1R D0R  A1L C0L  |  6594274 | ---- | 337 |  0  6  0 14  0  7  0  0  0  0  0 15  0  0  0
B1L H1L  C0R D1L  D1R C1R  E1L E0L  A0L B0R  | 11530505 | ---- |3000 |  2  0  0 11  3  3 10 12  2 10 10  6  5 18  5
B1L H1L  C0R E1L  D0R C1R  A1L B1R  B0L A0L  | 11679832 | ---- |1012 |  0  0  0  7 12  0  0  5 24 11  0  5 29 23  0
B1L H1L  C0R C1R  D1R B1R  E1L D1L  A0R E0L  | 11934239 | SRec |  15 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
B1L H1L  C0R C0L  E1L D0R  C1R D1R  B1R A0L  | 12689995 | BL_1 |2759 |  0  0  4  6  0  0 15  0  0  6 24  0  0  0 31
B1L H1L  C0L D1R  D1L C1L  E1R B1R  A0L E0R  | 14520827 | SRec |   4 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
B1L H1L  C0L C1R  D1L C1L  E1R D1R  A0L E0R  | 14521014 | SRec |   3 |  3  0  0  0  0  0  0  0  0  0  0  0  0  0  0
B1L H1L  C0L C1L  D1L C1L  E1R D1R  A0L E0R  | 14521098 | SRec |   3 |  3  0  0  0  0  0  0  0  0  0  0  0  0  0  0
B1L H1L  C0L C1L  D1L B1L  E1R D1R  A0L E0R  | 14521100 | SRec |   4 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
B1L H1L  C0L B1R  D1L C1L  E1R D1R  A0L E0R  | 14521240 | SRec |   4 |  4  0  0  0  0  0  0  0  0  0  0  0  0  0  0
B1L H1L  C0L D0R  D1L E0R  E1L A0L  C1R D0R  | 14576100 | ---- |2863 |  0  6  4 17  8 27  0 37 12 34 41 60  6 28 24
B1L H1L  C0L B0L  C1R D0R  A1L E0R  A0R E0R  | 15076017 | ---- |2349 |  2  2  3  9  0  0  8  7  0  7  0  0  0 10  0
B1L H1L  C0L D1L  D0R C1L  E1R A0L  A1L E0R  | 15764213 | ---- |3000 |  2  0 15 15 12 10 38 14 20 69  8 33 36 35 20

Machines writing 0 at first step (eliminated):
B0L H1L  C1R A1L  D1R A0L  E1L C0R  D0R E0L  | 17152796 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
B0L H1L  C1L D0R  B1R D0L  E1R A1L  C1L C0R  | 21462013 | ---- |3000 |  0  0  0 10  0 20 19  0  0 38  9 17  3 46  2
B0L H1L  C0R B1R  D1L B0R  E1L A0L  C1R C0L  | 23493752 | BL_2 |2797 |  0  0  6  7  9  0 15 15  9 13 16 10 32 13  8

```
NR_count =19
NR1_count=16
HNR_count=7

#### 1. Subset dm_2:

These machines reaches halt state from state B, tape value 1.

Nonregular machines:

```A0  A1   B0  B1   C0  C1   D0  D1   E0  E1   |    id    | type |SRcnt|          spectrum

C1L E1L  A1L H1L  D1R E0R  B1R E1R  C1R A0L  |   123831 | ---- |3000 |  0  4  4  0  0 20  4  0  7 15  0 68  4 38  5
C1L D0R  C0L H1L  D1R B1L  A1R E1L  E0L A0R  |  1375027 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L E0L  A1R H1L  D1R A0L  D0R B1R  C0L B0R  |  3198755 | ---- |3000 |  0  6 10 14 17 21 22 23 30 24 34 46 40 31 26
C1L E1R  D0R H1L  D1R A0L  A1L B1R  E0R C0L  |  3470230 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L E0R  D0R H1L  D1R A0L  A1L B1R  C0L E1R  |  3470440 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L C0R  D0L H1L  D1R E0L  C1L E0R  A1R B1L  |  5585454 | ---- |3000 |  0  0  0 10  0 20 19  0  0 38  9 17  3 46  2
C1L D0R  C0L H1L  D1R B1L  A1R E0L  A0R E1L  |  6237048 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A1L  E1R H1L  D1R D0R  B0R E0L  A0L C1R  |  6314131 | ---- |2985 |  2  0  0 11  3  3 13 11  3  9 13  5  6 15  6
C1L A0R  A1L H1L  D1R E1L  A1R D0R  E0L B0R  |  6929003 | ---- |3000 |  3  0  8 10  7 20 25 23 13 26 16  9 18 39 40
C1L B0R  A1R H1L  D1R E1L  E0L D0R  C0L A0R  |  7063528 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L B0R  E0R H1L  D1R A0L  C0L D0R  A1L B1R  |  7099251 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L E1L  E1R H1L  D1R C1R  B0L D0R  A0L A1L  |  7119815 | SRec |  13 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A1L  E1L H1L  D1R C1R  B0L D0R  A0L E1R  |  7120790 | SRec |   4 |  4  0  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A1L  E1L H1L  D1R E1R  B0L D0R  A0L C1R  |  7121860 | SRec |   4 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A1L  E1L H1L  D1R C1R  B0L D0R  A0L A1R  |  7124828 | SRec |   3 |  3  0  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L E1L  E1L H1L  D1R C1R  B0L D0R  A0L A1L  |  7126699 | SRec |   4 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L A1L  E1L H1L  D1R C1R  B0L D0R  A0L A1L  |  7126707 | SRec |   3 |  3  0  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L D0L  A1L H1L  D1R E0R  B0R C0R  C1R B0L  |  7915298 |  3N  | 112 |  0  6  0  0  0  0  0 10  0  8  0  0  0 10  0
C1L A1L  E1R H1L  D1R A0L  E1L B0R  C0L C0R  |  8450515 | BL_1 |2759 |  0  0  4  6  0  0 15  0  0  6 24  0  0  0 31
C1L C0R  E0R H1L  D1R E0L  A1R B0R  C0L E1L  |  8865978 | BL_1 |2752 |  0  0  6  9  9  0 14 16  9 12 17  8 32 12  8
C1L E0R  D1L H1L  D1R B0L  A0R A0L  A1R E1R  |  9510067 | BL_1 |2759 |  0  0  4  6  0  0 15  0  0  6 24  0  0  0 31
C1L B1R  A0R H1L  D1L B0R  E1R C0L  D0L E0R  | 10198926 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L E1R  D1R H1L  D1L C0L  A1R D1L  B1R A0R  | 12568936 | ---- | 319 |  0  6  0 14  0  7  0  0  0  0  0 15  0  0  0
C1L E0R  E0L H1L  D1L B0L  A1R A0L  A0R E1R  | 12876259 | BL_2 |2797 |  0  0  6  7  9  0 15 15  9 13 16 10 32 13  8
C1L B0R  E1R H1L  D1L A0L  B0L C0L  C1R D0R  | 14934318 |  3N  | 158 |  0  6  0  0  0  0  0  7  0  0  0  0  0  5  0
C1L E0L  D1R H1L  B1L E1L  A1R E1R  A1L D0R  | 17982461 | ---- |3000 |  0  4  4  0  0 20  4  0  7 15  0 68  4 38  5
C1L D0R  A0L H1L  A1R D0L  E1R B1L  C1L C0R  | 23741566 | ---- |3000 |  0  0  0 10  0 20 19  0  0 38  9 17  3 46  2
C1L E0L  A1R H1L  D0R E1L  D1R B1R  C0R A0L  | 28775330 |proved|  37 |  0  3  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L E0L  C1R H1L  D0R A1L  A1R E0R  B1R E0L  | 30515821 | ---- |3000 |  0  6  0 15 15  6 15 22 21 22 28 30 21 20 37
C1L D1R  E1L H1L  D0R C0L  A0R E0L  A1R B0L  | 31021905 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L D1R  A1R H1L  D0R E1L  B1R D0L  C0R E0L  | 31305274 |proved|   5 |  0  0  5  0  0  0  0  0  0  0  0  0  0  0  0
C1L B0R  E0R H1L  D0L C1L  E1L C0L  A1R C0R  | 33424333 | ---- |3000 |  2  5  9  7 20 29 49 56 52 68 48 59 64 51 54
C1L E0R  C0L H1L  D0L B0L  D1R A0R  A1R D1L  | 33938206 | ---- | 693 |  2 11  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L D1R  E1R H1L  D0L C0L  B1R A0R  A1R E1L  | 34364505 | ---- | 481 |  0  6  0 10  0  0  0  0  0  0  0  0  0  0  0
C1L D1R  E1R H1L  D0L C0L  B1R A0R  A1R A1L  | 34429669 | ---- | 466 |  0  7  0 11  0  0  0  0  0  0  0  0  0  0  0
C1L D1R  E1R H1L  D0L C0L  B1R A0R  A1R A0R  | 34508331 | ---- | 408 |  0  7  0 11  0  0  0  0  0  0  0  0  0  0  0
C1L E1R  D1R H1L  D0L C0L  B1R A1L  D1L A0R  | 34605254 | ---- |1273 |  0  6  0 10  0  0  0  0  0  0  0  0  0  0  0
C1L B0R  C1R H1L  D0L D0R  A1R E0L  D1L E1L  | 36278670 | ---- |2759 |  0  0  4  6  0  0 15  0  0  6 24  0  0  0 31
C1L B0R  A1R H1L  C0R D0L  E0L C1R  B1R D1L  | 39264109 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C1L E0L  D1R H1L  B0L A0L  A1R C0R  A1L B0R  | 39779768 |  3N  |  99 |  0  6  0  0  0  0  0  7  0  0  0  0  0  5  0
C1L C0L  D1L H1L  B0L D0R  E0R A1L  A1R E1R  | 40470734 | ---- |2890 |  2  0  0 11  3  3 10 13  2 10 10  6  5 17  5
C1L D0R  E0L H1L  A0R C0L  A1R B0L  D1R B1L  | 43147596 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
B1L D1L  C1R H1L  E1R D1R  E1L C0R  A1L D0L  | 43710027 | ---- |3000 |  0  4  4  0  0 20  4  0  7 15  0 68  4 38  5
B1L A0L  C1R H1L  C0R D0R  E1L B0L  E0L A1L  | 45963385 | ---- |3000 |  3  0  2  0  2  2  0  2  4  0  0  2  0  2  2
B1L A0R  C1L H1L  D1R A1L  A0L E1R  D0L E0R  | 47443779 |proved|   5 |  0  0  5  0  0  0  0  0  0  0  0  0  0  0  0
B1L E1R  C1L H1L  D1R B0L  D0L E0R  A0R D1L  | 47972394 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
B1L D1R  C1L H1L  A1R B0L  A0R E1L  E0L D0R  | 49258796 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
B1L D1R  C1L H1L  A1R B0L  A0R E0L  D0R E1L  | 49298410 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
B1L A0R  C1L H1L  D0L E1R  E1L A0L  C1R A0R  | 50233205 | ---- |3000 |  0  6  0 15 15  6 15 22 21 22 28 30 21 20 37
B1L E0R  C1L H1L  D0L C0L  D1R A0R  B0R E0R  | 50317033 | ---- |2287 |  2  2  3 10  0  2  8 10  0  7  0  0  0  7  0
B1L A0R  C0L H1L  C1R D1L  E1L A1R  B0L D0R  | 54769539 | ---- |3000 |  4  6  0  0 18 12 21 21 21 30 22 27 24 35 29

Machines writing 0 at first step (eliminated):
C0L A1L  A0R H1L  D1R A0L  E1R B0R  C1L C0R  | 56228561 | ---- |2797 |  0  0  6  7  9  0 15 15  9 13 16 10 32 13  8
C0L A1R  D0R H1L  D1R E0L  E1L B1R  C1L A0R  | 57044739 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L C0R  A1R H1L  D1R E0L  A1L B0R  C1L E1L  | 59041275 | BL_1 |2759 |  0  0  4  6  0  0 15  0  0  6 24  0  0  0 31
C0L E0R  E1R H1L  D1R A1L  A0L D0R  C1L B0R  | 60566578 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L C1L  A1R H1L  D1L A1L  E1R D1R  B0L E0R  | 61090715 | SRec |  13 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L D1R  A1L H1L  D1L C1L  E1R A1R  B0L E0R  | 61090972 | SRec |   4 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L C1R  A1L H1L  D1L C1L  E1R D1R  B0L E0R  | 61091140 | SRec |   3 |  3  0  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L C1L  A1L H1L  D1L C1L  E1R D1R  B0L E0R  | 61091224 | SRec |   3 |  3  0  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L C1L  A1L H1L  D1L A1L  E1R D1R  B0L E0R  | 61091228 | SRec |   4 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L A1R  A1L H1L  D1L C1L  E1R D1R  B0L E0R  | 61091368 | SRec |   4 |  4  0  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L D1R  A1R H1L  D1L C1L  E1R E0R  B0R A0L  | 61378854 | ---- |2985 |  2  0  0 11  3  3 13 11  3  9 13  5  6 15  6
C0L E1R  D1R H1L  B1R A1L  E1L B0R  E0R A0L  | 65669748 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L E1R  D1R H1L  B1R A1L  C1L B0R  E0R A0L  | 65749790 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L E0R  D1R H1L  B1R A1L  C1L B0R  A0L E1R  | 65753217 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L E1R  D1L H1L  B1L C0R  A1R C1L  A0L E0R  | 68849340 |proved|   5 |  0  0  5  0  0  0  0  0  0  0  0  0  0  0  0
C0L A0R  E0R H1L  A1R D0L  C1L B0R  D1L B1R  | 71780539 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L A1R  E1R H1L  D0L A0R  B1R C1L  D1L B0R  | 74783621 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
C0L A0R  E1L H1L  D0L A1R  B1L D0R  C1R D1L  | 75154490 |proved|   5 |  0  0  5  0  0  0  0  0  0  0  0  0  0  0  0
C0L A0R  E1R H1L  D0L E0R  A1R C1L  D1L B0R  | 75545380 | SRec |   5 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
B0L A0L  C1R H1L  D0R C0R  D1L E0L  B1R A0L  | 79447056 | ---- |2349 |  2  2  3  9  0  0  8  7  0  7  0  0  0 10  0
B0L A0R  C1R H1L  D0L D1L  E1L C1L  A1R E1R  | 79691224 | SRec |  15 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
B0L C0R  C1L H1L  D0R E1L  E1R D1R  A1L A0L  | 81688266 | ---- |3000 |  2  0  0 11  3  3 10 13  2 10 10  6  5 18  5
B0L A0R  C1L H1L  D0L E1R  E1L D1L  A1R C1R  | 81943391 | SRec |   4 |  2  4  0  0  0  0  0  0  0  0  0  0  0  0  0
B0L A0R  C1L H1L  D0L D1R  E1L D1L  A1R E1R  | 81943578 | SRec |   3 |  3  0  0  0  0  0  0  0  0  0  0  0  0  0  0
B0L A0R  C1L H1L  D0L D1L  E1L D1L  A1R E1R  | 81943662 | SRec |   3 |  3  0  0  0  0  0  0  0  0  0  0  0  0  0  0
B0L A0R  C1L H1L  D0L D1L  E1L C1L  A1R E1R  | 81943664 | SRec |   4 |  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
B0L A0R  C1L H1L  D0L C1R  E1L D1L  A1R E1R  | 81943806 | SRec |   4 |  4  0  0  0  0  0  0  0  0  0  0  0  0  0  0
```
NR_count =78
NR1_count=51
HNR_count=23

5. Some remarks:

The program is in active process of development and contains many redundant code.
Upper lists of nonregular machines are created with little older version.
If you scan TM(5) with current version, the lists must be shorter - NR1 must contain less than 100 machines.

I hope that my program methods are correct mathemathical proves for finitnes/infinitnes of the Turing Machines, but there may be some fatal error, making my results incorrect.

I will be happy to receive any comments or recomendations for future improvements.